In the fabrication of semiconductor integrated circuits and devices, an important goal has been the increased microminiaturization of these circuits and devices in order to produce structures having minimized size and maximized component density and speed. One step that is critical to these microminiaturization requirements is the definition of patterns in resist. Openings in the resist, formed by lithographic exposure and development processes, serve as a mask pattern for subsequent fabrication steps, such as etching, depositing metal patterns, or forming ion implanted regions. To achieve increased microminiaturization of integrated circuits, a lithography technique is needed which will produce a resist pattern with high resolution. In addition, in order to obtain a reasonable wafer throughout (i.e. wafers/hour), the process for exposing the resist pattern must be of reasonably high speed.
In the art of photolithography useful in the creation of resist patterns, ultraviolet radiation has been used for many years to expose a variety of known photoresist materials. While this technique is capable of providing a good throughput, it is not satisfactory for certain high resolution fabrication processes, such as those required for the fabrication of devices having submicrometer dimensions, since the ultraviolet radiation itself has limitations with respect to its diffraction and resolution characteristics which are dependent upon the wavelength of the ultraviolet radiation. For example, if a high resolution pattern is projected through an optical lens over a large area target, there will be distortions and reduced line resolution at the edges of the field due to the inherently small field of view of the lens. In order to overcome some of the limitations of optical lithography methods, other resist exposure technologies have been developed which use radiation with wavelengths shorter than those of ultraviolet radiation, namely electrons, x-rays, and ions. While all three of these latter techniques have demonstrated certain advantages over ultra-violet photolithography, both the x-ray and direct writing electron beam processes are time-consuming and do not readily lend themselves to the high throughput required for large scale batch fabrication processes.
Further, the direct writing electron beam process, in which an electron beam is scanned over a target in a predetermined pattern under computer control, has certain limitations when applied to large area targets. For example, the field of view of the focused electron beam is restricted by the resolution requirements for the device being formed. As the field size of a scanning electron beam is increased, there is an undesirable increase in distortions and decrease in line resolution due to beam defocusing at the edges of the field. In addition, deflection aberrations of the electron beam cause distortion of the shape of the electron beam and consequently produce pattern distortions and reduced pattern resolution. Finally, it is complex to produce and implement high speed electronics for the deflection of an electron beam over a large area target. Thus, a distinct limitation of both optical projection lithography and direct writing electron beam lithography is that their fields of view are inherently limited and cannot be chosen to optimize process parameters, such as throughput.
Some of the above-mentioned problems are overcome by the use of an electron projection lithographic process. However, the latter process exhibits adverse proximity effects when exposing closely spaced pattern features of varying size. The ion beam lithographic technique has been found to be a method which produces high resolution patterns at high speed, does not have an adverse proximity effect, does not have an inherent limit to the field of view, and is the subject of this invention.
The utilization of collimated ion beams to expose certain known and commerically available polymer (resist) materials is generally known in the art of ion beam lithography and is disclosed, for example, in an article entitled "Focused Ion Beams in Microfabrication," by R. L. Seliger and W. P. Fleming, in The Journal of Applied Physics, Vol. 45, No. 3, March 1974 and in U.S. Pat. No. 4,101,782 and No. 4,158,141, both assigned to the present assignee. The processes of these latter-referenced patents make use of an off-contact technique in which there is a space between the mask and the target resist. One advantage of such an off-contact process is that the mask is prevented from being contaminated during use and can be reused many times. While the prior art ion beam lithography processes are satisfactory for the exposure of a wafer having a small area, e.g. one square centimeter, the processes noted above do not specifically address the optimum technique for exposing large area wafers, e.g. four inches in diameter. In particular, in the exposure of a large area wafer by an off-contact process, the diameters of both the beam and the mask, which are critical parameters, has not been discussed. The optimum choice of these diameters and a process and apparatus for achieving large wafer exposure are required for the practical application of an ion beam lithography process.
If the beam and mask diameters coincide with the diameter of the wafer (e.g. four inches), several problems arise. First of all, it is difficult to produce a collimated beam of large diameter that would be required to maintain a minimum lateral beam displacement of less than 0.1 micrometer at the target in order to produce the desired high-resolution patterns. Secondly, fabrication of a large mask requires more time, produces a lower yield, and has a higher cost than fabrication of a smaller mask. Furthermore, a dimensional tolerance in the mask of 0.1 micrometer is required for the production of devices having submicrometer dimensions. In order to maintain this tolerance over a mask of four inches in diameter, a tolerance of one part in 1.times.10.sup.6 would have to be maintained over the entire mask area, which would be difficult to achieve.
Finally, there exists the problem of lateral wafer distortions which occur when the wafer becomes heated and expands as a result of certain high temperature processing steps, such as diffusion, thermal oxidation, or epitaxial growth. It is estimated that even with careful control of thermal processes, silicon wafers will have an in-plane distortion, or "runout," of approximately one part in 1.times.10.sup.5, or 0.1 micrometer in one centimeter. This distortion must be taken into consideration during the multiple masking and alignment procedures usually required in the fabrication of a semiconductor device or inegrated circuit. For example, benchmarks may be formed at the periphery of a wafer for purposes of alignment when using a mask which is the same size as the wafer. The mask and wafer are aligned by the benchmarks and a processing step, such as etching, is performed. Then, the wafer may be subjected to an oxidation process at a high temperature (i.e. 1100.degree. to 1200.degree. C.). During heating, the wafer expands, and when the wafer is subsequently cooled, it contracts. However, such expansion and contraction results in distortion of the geometry of the wafer. The total wafer may increase or decrease in size or the wafer may increase in length along one axis and decrease in length along another axis, resulting in an elliptical shape. As the wafer becomes distorted in shape, the benchmarks change position on the wafer. Thus, the original benchmarks formed on the wafer cannot be used for alignment in a subsequent processing step. In addition, any structures, such as gates, which were formed on the wafer prior to a process such as oxidation have also changed position or had their geometries distorted as a result of the expansion and contraction of the wafer. Thus, it is difficult to align these structures with the next level of masking required for forming these desired device. For the reasons, choosing the beam and mask diameters to be equal to the wafer diameter, while yielding a high throughput, does not readily provide the desired high resolution required for microminiaturization of integrated circuits and devices.
A possible alternative procedure for the exposure of a large area wafer uses an ion beam of small cross-section (e.g. one centimeter.sup.2) and a mask which is equal in size to the wafer. The ion beam is then raster scanned over the mask and wafer in order to expose the resist on the total wafer, using a form of serial ion exposure. This procedure has the same disadvantages as noted above with respect to difficulty in fabricating a large area mask, difficulty in maintaining required dimensional tolerances in the mask, and the problem of lateral wafer distortion which occur in the process which uses a wide collimated beam. In addition, the process which uses a narrow, raster scanned beam requires particularly close control of the deflection angle of the ion beam in order to replicate the desired pattern accurately. Although satisfactory control of the ion beam deflection can be achieved, a complex and expensive system is usually required.